`timescale 100ms/10ms
//the first setp:defining the ports
//Input signals, which act as stimuli, should be declared as 'reg' type; 
//while output signals should be declared as 'wire' type.


module tb_traffic_ex_lights;
	reg clk;
	reg reset;
	reg press;
	wire [2:0] lights_c;
	wire [2:0] lights_p;



	//the sencond setp:Module Instantiation
	//instantiating the module under test
	traffic_lights_ex_top top_inst(
		.clk(clk),
		.reset(reset),
		.press(press),
		.lights_c(lights_c),
		.lights_p(lights_p));
	
	// the third step:writing the stimuli for a digital circuit test
	//singal of "reset"
	initial begin
        clk = 0;
        reset = 1;
		  #22
		  reset = 0;
		  #2000
		  reset = 1;
		  #12
		  reset = 0;
		  #5000
		  $stop;
    end

	//singal of "press"
	 initial begin
        press = 0;
		  #60
		  press = 1;
		  #60
		  press = 0;
		  #100
		  press = 1;
		  #12
		  press = 0;
		  #1000
		  press = 1;
		  #10
		  press = 0;
		  #10
		  press = 1;
		  #10
		  press = 1;
		  #10
		  press = 0;
		  #10
		  press = 1;
		  #10
		  press =0;
		  #3000
		  press = 1;
    end
	
	//singal of "clk"
    always #5 clk = ~clk;

	
	initial begin
    	$dumpfile("wave.vcd"); // 声明输出文件名
    	$dumpvars(0, tb_traffic_ex_lights); // 记录信号，可以根据需要记录指定级别的信号
	end
	
	 
endmodule
